1/9 december 2003 STW11NK100Z n-channel 1000v - 1.1 w -8.3ato-247 zener-protected supermesh?power mosfet n typical r ds (on) = 1.1 w n extremely high dv/dt capability n 100% avalanche tested n gate charge minimized n very low intrinsic capacitances n very good manufacturing repeatibility description the supermesh? series is obtained through an extreme optimization of sts well established strip- based powermesh? layout. in addition to pushing on-resistance significantly down, special care is tak- en to ensure a very good dv/dt capability for the most demanding applications. such series comple- ments st full range of high voltage mosfets in- cluding revolutionary mdmesh? products. applications n high current, high speed switching n ideal for off-line power supplies ordering information type v dss r ds(on) i d pw STW11NK100Z 1000 v < 1.38 w 8.3 a 230 w sales type marking package packaging STW11NK100Z w11nk100z to-247 tube to-247 1 2 3 internal schematic diagram
STW11NK100Z 2/9 absolute maximum ratings ( ) pulsewidthlimitedbysafeoperatingarea (1) i sd 8.3a, di/dt 200a/s, v dd v (br)dss ,t j t jmax. (*) limited only by maximum temperature allowed thermal data avalanche characteristics gate-source zener diode protection features of gate-to-source zener diodes the built-in back-to-back zener diodes have specifically been designed to enhance not only the devices esd capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. in this respect the zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the devices integrity. these integrated zener diodes thus avoid the usage of external components. symbol parameter value unit v ds drain-source voltage (v gs =0) 1000 v v dgr drain-gate voltage (r gs =20k w ) 1000 v v gs gate- source voltage 30 v i d drain current (continuous) at t c = 25c 8.3 a i d drain current (continuous) at t c = 100c 5.2 a i dm ( ) drain current (pulsed) 33.2 a p tot total dissipation at t c = 25c 230 w derating factor 1.85 w/c v esd(g-s) gate source esd(hbm-c=100pf, r=1.5k w) 6000 v dv/dt (1) peak diode recovery voltage slope 4.5 v/ns t j t stg operating junction temperature storage temperature -55 to 150 c rthj-case thermal resistance junction-case max 0.54 c/w rthj-amb t l thermal resistance junction-ambient max maximum lead temperature for soldering purpose 50 300 c/w c symbol parameter max value unit i ar avalanche current, repetitive or not-repetitive (pulse width limited by t j max) 8.3 a e as single pulse avalanche energy (starting t j = 25 c, i d =i ar ,v dd =50v) 550 mj symbol parameter test conditions min. typ. max. unit bv gso gate-source breakdown voltage igs= 1ma (open drain) 30 v
3/9 STW11NK100Z electrical characteristics (t case =25c unless otherwise specified) on/off dynamic source drain diode note: 1. pulsed: pulse duration = 300 s, duty cycle 1.5 %. 2. pulse width limited by safe operating area. 3. c oss eq. is defined as a constant equivalent capacitance giving the same charging time as c oss when v ds increases from 0 to 80% v dss . symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d =1ma,v gs = 0 1000 v i dss zero gate voltage drain current (v gs =0) v ds = max rating v ds = max rating, t c = 125 c 1 50 a a i gss gate-body leakage current (v ds =0) v gs = 20v 10 a v gs(th) gate threshold voltage v ds =v gs ,i d = 100 a 3 3.75 4.5 v r ds(on) static drain-source on resistance v gs =10v,i d = 4.15 a 1.1 1.38 w symbol parameter test conditions min. typ. max. unit g fs (1) forward transconductance v ds =15v , i d = 4.15 a 9 s c iss c oss c rss input capacitance output capacitance reverse transfer capacitance v ds =25v,f=1mhz,v gs = 0 3500 270 60 pf pf pf c oss eq. (3) equivalent output capacitance v gs =0v,v ds = 0v to 500v 170 pf t d(on) t r t d(off) t f turn-on delay time rise time turn-off delay time fall time v dd =800v,i d =8a r g = 4.7 w v gs =10v (resistive load see, figure 3) 27 18 98 55 ns ns ns ns q g q gs q gd total gate charge gate-source charge gate-drain charge v dd =800v,i d =8a, v gs =10v 113 18 60 162 nc nc nc symbol parameter test conditions min. typ. max. unit i sd i sdm (2) source-drain current source-drain current (pulsed) 8.3 33.2 a a v sd (1) forward on voltage i sd = 8.3 a, v gs =0 1.6 v t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 8 a, di/dt = 100 a/s v dd =80v,t j = 25c (see test circuit, figure 5) 560 4.48 16 ns c a t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 8 a, di/dt = 100 a/s v dd =80v,t j = 150c (see test circuit, figure 5) 620 4.57 16 ns c a
STW11NK100Z 4/9 thermal impedance transconductance transfer characteristics output characteristics safe operating area static drain-source on resistance
5/9 STW11NK100Z normalized bvdss vs temperature normalized on resistance vs temperature capacitance variations gate charge vs gate-source voltage normalized gate threshold voltage vs temp. source-drain diode forward characteristics
STW11NK100Z 6/9 maximum avalanche energy vs temperature
7/9 STW11NK100Z fig. 5: test circuit for inductive load switching and diode recovery times fig. 4: gate charge test circuit fig. 2: unclamped inductive waveform fig. 1: unclamped inductive load test circuit fig. 3: switching times test circuit for resistive load
STW11NK100Z 8/9 dim. mm. inch min. typ max. min. typ. max. a 4.85 5.15 0.19 0.20 a1 2.20 2.60 0.086 0.102 b 1.0 1.40 0.039 0.055 b1 2.0 2.40 0.079 0.094 b2 3.0 3.40 0.118 0.134 c 0.40 0.80 0.015 0.03 d 19.85 20.15 0.781 0.793 e 15.45 15.75 0.608 0.620 e5.45 0.214 l 14.20 14.80 0.560 0.582 l1 3.70 4.30 0.14 0.17 l2 18.50 0.728 ?p 3.55 3.65 0.140 0.143 ?r 4.50 5.50 0.177 0.216 s5.50 0.216 to-247 mechanical data
9/9 STW11NK100Z information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco singapore - spain - sweden - switzerland - united kingdom - united states. ? http://www.st.com
|
